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| HD74ALVC1G80 Single Positive Edge-triggered D-type Flip Flop REJ03D0127-0300Z (Previous ADE-205-638B (Z)) Rev.3.00 Nov.12.2003 Description The HD74ALVC1G80 has D-type flip flop in a 5 pin package. The input data is transferred to the output at the rising edge of clock pulse CLK. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features * The basic gate function is lined up as Renesas uni logic series. * Supplied on emboss taping for high-speed automatic mounting. * Supply voltage range : 1.2 to 3.6 V Operating temperature range : -40 to +85C * All inputs VIH (Max.) = 3.6 V (@VCC = 0 V to 3.6 V) All outputs VO (Max.) = 3.6 V (@VCC = 0 V) * Output current 2 mA (@VCC = 1.2 V) 4 mA (@VCC = 1.4 V to 1.6 V) 6 mA (@VCC = 1.65 V to 1.95 V) 18 mA (@VCC = 2.3 V to 2.7 V) 24 mA (@VCC = 3.0 V to 3.6 V) * Ordering Information Package Part Name HD74ALVC1G80VSE Package Type VSON-5 pin Package Code TNP-5DV Abbreviation VS Taping Abbreviation (Quantity) E (3,000 pcs/reel) Rev.3.00, Nov.12.2003, page 1 of 10 HD74ALVC1G80 Outline and Article Indication * HD74ALVC1G80 Marking A G VSON-5 = Control code Function Table Inputs CLK L H: L: X: : Q0 : D H L X Output Q L H Q0 High level Low level Immaterial Low to high transition Level of Q before the indicated steady input conditions were established. Rev.3.00, Nov.12.2003, page 2 of 10 HD74ALVC1G80 Pin Arrangement D 1 5 VCC CLK 2 GND 3 4 Q (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 *1, 2 Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VCC+0.5 -0.5 to 4.6 -50 50 50 100 200 -65 to 150 Unit V V V Conditions Output voltage range Output : H or L VCC : OFF Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25C (in still air) *3 Storage temperature Notes: mA mA mA mA mW C VI < 0 VO < 0 or VO > VCC VO = 0 to VCC The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C. Rev.3.00, Nov.12.2003, page 3 of 10 HD74ALVC1G80 Recommended Operating Conditions Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOH Min 1.2 0 0 IOL Input transition rise or fall rate t / v Ta 0 0 Operating free-air temperature -40 Note: Unused or floating inputs must be held high or low. Max 3.6 3.6 VCC -2 -4 -6 -18 -24 2 4 6 18 24 20 10 85 C ns / V Unit V V V mA VCC = 1.2 V VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 1.2 V VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 1.2 to 2.7 V VCC = 3.30.3 V Conditions Logic Diagram CLK C C C Q C TG C C C D TG TG TG C C C Rev.3.00, Nov.12.2003, page 4 of 10 HD74ALVC1G80 Electrical Characteristics (Ta = -40 to 85C) Item Input voltage Symbol VIH VCC (V) * 1.2 1.4 to 1.6 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 VIL 1.2 1.4 to 1.6 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 Output voltage VOH Min to Max 1.2 1.4 1.65 2.3 3.0 VOL Min to Max 1.2 1.4 1.65 2.3 3.0 Input current Quiescent supply current Output leakage current Input capacitance IIN ICC IOFF CIN 3.6 3.6 0 3.3 Min VCCx0.7 VCCx0.7 1.7 2.0 VCC-0.2 0.9 1.1 1.2 1.7 2.2 Typ 4.0 Max VCCx0.25 VCCx0.3 VCCx0.3 0.7 0.8 0.2 0.3 0.3 0.3 0.55 0.55 5 10 5 A A A pF V IOH = -100 A IOH = -2 mA IOH = -4 mA IOH = -6 mA IOH = -18 mA IOH = -24 mA IOL = 100 A IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 18 mA IOL = 24 mA VIN = 3.6 V or GND VIN = VCC or GND, IO = 0 VIN or VO = 0 to 3.6 V VIN = VCC or GND Unit V Test conditions VCCx0.75 Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.3.00, Nov.12.2003, page 5 of 10 HD74ALVC1G80 Switching Characteristics (Ta = -40 to 85C) VCC = 1.2 V Item Maximum clock frequency Propagation delay time Setup time Hold time Pulse width Symbol fmax tPLH tPHL tsu th tw Min Typ 200 7.3 4.5 -4.5 2.0 Max Unit MHz ns ns ns ns CLK "H" or "L" Test conditions CL = 15 pF CL = 15 pF CLK D Q FROM (Input) TO (Output) VCC = 1.50.1 V Item Maximum clock frequency Propagation delay time Setup time Hold time Pulse width Symbol fmax tPLH tPHL tsu th tw Min 100 2.0 4.5 0.0 3.5 Typ 350 Max 8.0 Unit MHz ns ns ns ns CLK "H" or "L" Test conditions CL = 15 pF CL = 15 pF CLK D Q FROM (Input) TO (Output) VCC = 1.80.15 V Item Maximum clock frequency Propagation delay time Setup time Hold time Pulse width Symbol fmax tPLH tPHL tsu th tw Min 160 1.5 3.5 0.0 2.5 Typ 350 Max 7.0 Unit MHz ns ns ns ns CLK "H" or "L" Test conditions CL = 30 pF CL = 30 pF CLK D Q FROM (Input) TO (Output) Rev.3.00, Nov.12.2003, page 6 of 10 HD74ALVC1G80 Switching Characteristics (cont) VCC = 2.50.2 V Item Maximum clock frequency Propagation delay time Setup time Hold time Pulse width Symbol fmax tPLH tPHL tsu th tw Min 160 1.0 2.5 0.0 2.5 Typ 400 Max 4.0 Unit MHz ns ns ns ns CLK "H" or "L" Test conditions CL = 30 pF CL = 30 pF CLK D Q FROM (Input) TO (Output) VCC = 3.30.3 V Item Maximum clock frequency Propagation delay time Setup time Hold time Pulse width Symbol fmax tPLH tPHL tsu th tw Min 200 1.0 2.0 0.0 2.0 Typ 450 Max 3.0 Unit MHz ns ns ns ns CLK "H" or "L" Test conditions CL = 30 pF CL = 30 pF CLK D Q FROM (Input) TO (Output) Operating Characteristics (Ta = 25C) Item Power dissipation capacitance Symbol CPD VCC (V) 1.5 1.8 2.5 3.3 Min Typ 7.5 7.5 8.0 11.0 Max Unit pF Test conditions f = 10 MHz Rev.3.00, Nov.12.2003, page 7 of 10 HD74ALVC1G80 Test Circuit VCC Input Pulse Generator Zout = 50 Input D Q CL RL Output Q Pulse Generator Zout = 50 CLK Symbol RL CL V CC = 1.2 V, V = 2.50.2 V, V = 1.80.15 V CC 1.50.1 V CC 3.30.3 V 2.0 k 15 pF 1.0 k 30 pF 500 30 pF Note: CL includes probe and jig capacitance. Rev.3.00, Nov.12.2003, page 8 of 10 HD74ALVC1G80 * Waveform - 1 tr 90 % 10 % t su Vref th 90 % tf VIH 10 % GND Timming input Data input VIH Vref tw VIH Vref GND Input Vref Vref GND * Waveform - 2 tr 90 % Vref 10 % t PLH 10 % GND 90 % tf VIH Input VOH Same-phase output t PHL VOH Opposite-phase output Vref VOL V CC = 1.2 V, 1.50.1 V, V CC = 2.50.2 V 1.80.15 V 2.0 ns VCC 50% 2.5 ns VCC 50% Vref VOL Symbol tr / t f V IH V ref V CC = 3.30.3 V 2.5 ns 2.7 V 1.5 V Note: Input waveform : PRR = 10 MHz, duty cycle 50% Rev.3.00, Nov.12.2003, page 9 of 10 HD74ALVC1G80 Package Dimensions 1.6 0.05 Unit: mm (0.1) Package Code JEDEC JEITA Mass (reference value) TNP-5DV 0.002 g 1.6 0.05 1.2 0.1 0.2 5 - 0.2 -0.05 +0.1 0.2 0.5 1.0 0.1 0.5 0.6 MAX Rev.3.00, Nov.12.2003, page 10 of 10 0.12 -0.05 +0.1 (0.1) Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 http://www.renesas.com (c) 2003. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 1.0 |
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